Introduction to Verilog
Digital Design covered what to build — truth tables, minimized Boolean expressions, state diagrams — entirely on paper. Verilog is one of the two dominant…
Modules and Ports
A module is Verilog's fundamental unit of hardware: a self-contained block with a name, a set of ports (its connections to the outside world), and a…
Verilog Data Types
Verilog has two fundamentally different categories of data type — nets and variables — and the distinction isn't cosmetic: it reflects whether a signal is…
Operators and Expressions
Verilog's operators are how the right-hand side of an assign, or any expression inside a procedural block, gets evaluated. Most will look familiar from…
Gate-Level Modeling
Gate-level modeling describes a circuit as an explicit netlist of primitive logic gates wired together — the closest Verilog gets to drawing a schematic…
Dataflow Modeling
Dataflow modeling describes a circuit as one or more equations relating outputs to inputs, using the assign keyword instead of naming individual gates…
Behavioral Modeling
Behavioral modeling describes a circuit's behavior with procedural code — if, case, loops — inside initial or always blocks, rather than as a gate netlist…
Blocking vs. Nonblocking Assignment
Verilog has two assignment operators that look almost interchangeable — = and <= — but describe genuinely different hardware update behavior. Using the…
Conditional and Case Statements
if/else and case are the two decision-making constructs used inside procedural (always/initial) blocks. They can often express the same logic, but they…
Loops
Verilog has four loop constructs — for, while, repeat, forever — all legal in simulation, but only some of them (and only under specific conditions) mean…
Functions and Tasks
Functions and tasks package a piece of procedural code under a name, so it can be called from multiple places instead of copy-pasted. They look similar…
Timing Controls
Verilog has three ways to make a procedural statement wait: #delay, @(event), and wait. All three are essential for writing a simulation model or…
Combinational vs. Sequential always Blocks
Every rule of thumb mentioned so far — use @(*) and blocking assignment for combinational logic, use @(posedge clk) and nonblocking assignment for…
FSM Coding Styles
Digital Design's FSM Fundamentals designed a Moore-machine sequence detector — asserting out=1 the cycle after seeing two consecutive 1s on serial input X…
Parameters and generate
Data Types built a 4-bit ripple-carry adder by hand-instantiating four full_adder copies, one line per bit. That approach doesn't scale — an 8-bit…
Arrays and Memories
Data Types introduced the array declaration reg [7:0] mem [0:255]; — 256 elements, each 8 bits wide — without saying what it's for. This page is that…
System Tasks and Compiler Directives
System tasks (prefixed $) and compiler directives (prefixed `) are Verilog's built-in tooling vocabulary — not hardware description at all, but the…
Simple Testbenches
Every module in this topic so far has been the design under test (DUT) — the thing meant to become real hardware. A testbench is different: it's Verilog…
Example Walkthrough: Verilog Frame Receiver
Digital Design's FSM Example Walkthrough designed a complete serial frame receiver controller — state diagram, state table, Gray-coded state assignment…