Introduction to SystemVerilog
Verilog is enough to describe real, synthesizable hardware — but writing a thorough testbench in plain Verilog is painful. There's no way to bundle…
SystemVerilog Data Types
Verilog's data types split into nets (wire) and variables (reg), and the compiler enforces which one goes where — assigned-in-a-procedural-block signals…
Structures and Unions
Plain Verilog has no way to group related signals into one named, reusable type — a full adder's three inputs (a, b, cin) are just three separate…
Arrays
Verilog's Arrays and Memories page introduced Verilog's one array form — reg [7:0] mem [0:255] — a fixed-size collection declared at compile time, with no…
Dynamic and Associative Arrays
The previous page's arrays all had a size fixed at compile time. A testbench, though, often doesn't know how many transactions a test will generate until…
Procedural Block Enhancements
Combinational vs. Sequential always Blocks laid out the rule synthesis tools use to turn a plain always block into either combinational logic, a latch, or…
Control Flow
Verilog's Loops page covered for, while, repeat, and forever. SystemVerilog adds a small set of control-flow constructs on top — none of them enable…
Tasks and Functions Enhancements
Verilog's Functions and Tasks page covered the core rules — functions return one value in zero time, tasks can consume time and have multiple outputs, and…
Interfaces
Verilog's Modules and Ports showed named port connection (.port_name(signal_name)) as the safe way to wire a module instance — but that safety comes at a…
Packages and Scope
System Tasks and Compiler Directives covered include — textually pasting one file's contents into another at compile time. That works, but it has a real…
Classes Basics
Every page before this one has covered types that hold data — signals, structs, arrays. None of them bundle behavior with that data, and none of them have…
Inheritance and Polymorphism
Classes Basics built one transaction class. Real testbenches need families of related classes — a base transaction, and specialized variants (a read…
Encapsulation and Abstraction
Every property and method in Classes Basics and Inheritance and Polymorphism has been freely readable and writable from anywhere the class's handle is…
Static and Parameterized Classes
Every property covered so far belongs to one specific object — tr1.data and tr2.data are two independent pieces of storage, even though both objects came…
Randomization and Constraints
A plain Verilog testbench generates stimulus by hand — a directed sequence of specific values the test writer chose. That finds exactly the bugs the…
Constraint Techniques
Randomization and Constraints covered ordinary (hard) constraints — rules randomize() is never allowed to violate. Real testbenches need a few more tools…
Processes and Fork-Join
Every initial/always block in Verilog already runs concurrently with every other one — that's the "concurrent hardware description" idea from Verilog's…
Interprocess Communication
Processes and Fork-Join showed how to run multiple processes concurrently, but said nothing about how they coordinate — how a driver process hands a…
Immediate Assertions
Checking that a signal has an expected value, in plain Verilog, means writing an if statement and manually deciding what to do when it's false — print an…
Concurrent Assertions
Immediate Assertions check a condition at one instant — the moment the assert statement executes. Many real hardware rules aren't instantaneous at all…
Functional Coverage
Randomization and Constraints generates legal stimulus automatically — but that raises an immediate follow-up question a directed test never has to ask…
Clocking Blocks and Program Blocks
Every construct in this curriculum so far has been about what to write. This page is about a subtler, easy-to-miss problem: when, exactly, testbench code…
Example Walkthrough: Full Adder Testbench
Verilog's own Example Walkthrough closed that topic with a full RTL implementation of a serial frame receiver, driven by a plain-Verilog, directed…