FPGA Basics: LUTs & Configurable Fabric

An FPGA (Field-Programmable Gate Array) scales the ideas from the previous two pages — a lookup table's ability to implement any function, and a programmable interconnect's ability to wire arrays together — up by orders of magnitude, and adds storage elements into the same reconfigurable fabric. The result is a single chip that can be configured, after manufacture ("in the field"), to implement almost any digital circuit at all — not just fixed-function AND-OR logic, but arbitrary multi-level combinational logic combined with registers, exactly the kind of designs built throughout this entire topic.

The lookup table (LUT)

An FPGA's basic combinational element is a LUT (lookup table) — and this isn't a new idea: it's precisely the MUX-as-universal-function trick from Multiplexers, Decoders & Comparators, where wiring a truth table's output column directly onto a 2ⁿ-to-1 MUX's data inputs implements any n-input Boolean function with no gates beyond the MUX itself. A typical FPGA LUT is a small 2ⁿ-to-1 MUX (commonly 4 to 6 select lines in real devices) whose data inputs are loaded from configuration memory — tiny SRAM bits set when the FPGA is configured — rather than hardwired:

This is functionally identical to the ROM idea from two pages back — an addressed lookup table implementing any function of its inputs — just repurposed as a small, per-gate primitive instead of one large central memory array, and reprogrammed by loading new values into that same configuration SRAM rather than blowing fuses or trapping floating-gate charge.

The configurable logic block (CLB) / slice

A LUT alone is purely combinational. Pairing one LUT with one D flip-flop — reusing exactly the flip-flop from Latches & Flip-Flops, with the LUT feeding the flip-flop's D input and a configuration bit choosing whether the block's output comes from the LUT directly or from the registered flip-flop output — gives a single reconfigurable unit capable of acting as either combinational logic or a storage element, commonly called a slice or logic cell:

Real FPGAs group several slices together into a larger configurable logic block (CLB), along with local routing and sometimes dedicated carry logic (a fast, hardwired carry-chain path is a common special case, since ripple-carry addition — from Combinational Logic Design — is common enough across real designs to be worth a dedicated fast path rather than routing it through general LUT fabric). A modern FPGA contains many thousands to millions of these slices, tiled across the chip.

Interconnect and I/O

Slices alone don't make a useful device — they need to be wired to each other according to whatever circuit is being implemented, and that wiring itself has to be reconfigurable. FPGA routing fabric is a grid of wire segments with programmable switches — an FPGA-scale generalization of the programmable AND/OR array connections from PLA and PAL — at their intersections, configured to connect specific slice outputs to specific slice inputs across the chip. I/O blocks around the chip's periphery are similarly configurable, adapting the chip's physical pins to whatever voltage standards and directions (input, output, or bidirectional) the design needs.

All of this configuration — every LUT's contents, every flip-flop's use-or-bypass setting, every routing switch's state — lives in on-chip SRAM configuration memory, loaded from an external bitstream file every time the FPGA powers up (since SRAM, unlike the non-volatile ROM technologies from two pages back, loses its contents without power). That's the direct practical meaning of "field-programmable": the same physical chip can implement a completely different circuit tomorrow, just by loading a different bitstream — no new silicon, no factory involvement, in sharp contrast to a mask ROM or a Mask-ROM-style ASIC.

FPGA vs. ASIC, briefly

An ASIC (Application-Specific Integrated Circuit) implements a fixed design directly in custom silicon, with no reconfigurable LUT/routing overhead at all — faster, lower-power, and cheaper per unit at high volume, but committing to a design that can never change once fabricated, and with a very expensive, slow (many months) manufacturing turnaround for any revision. An FPGA trades some of that speed/power/cost efficiency for reconfigurability and near-instant iteration — reprogram and retest in seconds, not months — which is why FPGAs dominate prototyping, low/medium-volume products, and anywhere a design might need to change after deployment, while ASICs dominate high-volume, performance- or power-critical, finalized designs. Every concept covered across this entire Digital Design topic — Boolean logic, combinational building blocks, sequential storage, FSMs — is exactly what eventually gets synthesized onto one platform or the other; the HDL topics elsewhere on this site are where that synthesis process itself is covered in detail.

What's next

This closes out memory and programmable logic — from a single SRAM/DRAM storage cell, through ROM's lookup-table view of combinational logic, through PLA/PAL's programmable AND-OR arrays, up to an FPGA's field-reconfigurable fabric of LUTs, flip-flops, and routing. The remaining scoped-out topics from the original curriculum plan — logic families' electrical characteristics, asynchronous sequential circuit design, and static/dynamic hazards — remain available as future sections; see DEVLOG.md for the current state of the curriculum.