Introduction to Verification
Digital Design's own introduction already used the word once, in passing: "Verification / UVM cover how to prove the RTL you wrote matches the design you…
The Cost of Bugs
Every verification technique in this curriculum costs real engineering time. None of it is free, and none of it is optional busywork — this page makes the…
Verification Methodologies Landscape
The Cost of Bugs made the case for spending real effort on verification. This page surveys the actual menu of techniques that effort buys — what each one…
The CDV Loop
Every generator, driver, monitor, and scoreboard built across Testbench and UVM exists to run one specific, named methodology: coverage-driven…
Code Coverage
Functional coverage is user-defined — a covergroup only tracks what someone explicitly wrote a coverpoint for. Code coverage is the opposite: a tool…
Functional Coverage Strategy
SystemVerilog's own functional coverage page covers covergroup/coverpoint/cross syntax. It doesn't cover the judgment calls that decide whether a…
Coverage Closure
The CDV Loop ends with "repeat until signoff targets met" — the question this page actually answers. Closure isn't a single event; it's a process with its…
Formal Verification Introduction
Everything in Sections A and B — directed tests, constrained-random stimulus, coverage — shares one structural limit: each is a sample. However many…
Property and Equivalence Checking
Formal Verification Introduction covered the mathematics; this page covers the two genuinely distinct problems formal tools are actually pointed at in a…
Clock Domain Crossing Verification
Every technique in Sections A through C shares one quiet assumption: that a signal sampled by a flip-flop actually obeys that flip-flop's setup and hold…
Reset Domain Crossing Verification
Clock Domain Crossing Verification covered metastability on ordinary data signals crossing clock domains. A reset signal crossing into a domain it wasn't…
RTL Linting
Every technique covered so far — CDV, formal, CDC, RDC — needs the design to actually simulate or run through a formal engine first. Linting doesn't: it's…
Gate-Level Simulation & X-Propagation
Every simulation in Testbench and UVM ran against RTL — behavioral, unsynthesized, no real gate delays. Gate-level simulation (GLS) runs the same…
Power-Aware Verification
Every technique so far assumed the whole design is powered, all the time. A real chip with multiple power domains — parts of it deliberately switched off…
Timing Verification and STA
Every other page in this section checks functional correctness — does the design do the right thing. Static Timing Analysis (STA) checks something no…
The Verification Plan
Every technique across Sections A through D — coverage, formal, CDC, linting, GLS, power-aware, timing — answers "is this specific thing correct." None of…
Regression and Bug Management
The Verification Plan names what needs checking. This page covers the operational machinery that actually runs those checks continuously, catches when a…
Verification Signoff and Metrics
Coverage Closure already made the core point for one metric: a coverage percentage alone is a decision input, never a decision. This page extends that to…
Verification IP
Every reusable component built across Testbench and UVM — a driver, monitor, scoreboard, sequence library, all bundled as one agent — has a name in…
Example Walkthrough: Verifying the FIFO
Every mechanism, methodology, and process across this curriculum's 20 pages now exists. This capstone doesn't introduce anything new — it applies all of…