Introduction to Testbench
Simple Testbenches built the smallest testbench that can possibly exist: one initial block, a handful of directed stimulus lines, an if/else comparing the…
From Simple to Layered
Two testbenches already exist elsewhere on this site, for the same full adder. Both are worth looking at honestly, one more time, before building anything…
The FIFO Testbench Plan
Every remaining page in this topic builds one piece of a single testbench, for one DUT. This page introduces that DUT, the interface connecting to it, and…
The Transaction Class
Every component in the block diagram from The FIFO Testbench Plan — generator, driver, monitor, scoreboard — passes the same thing back and forth: one…
The Generator
From Simple to Layered flagged this as the first concrete gap: SystemVerilog's own capstone randomized and put()-ed transactions directly inside tb_top's…
The Virtual Interface Bridge
The generator and its mailbox, built in Section B, live entirely inside class-based, procedural code — no module, no hierarchy, no physical connection to…
Testbench: The Driver
The generator has transactions waiting in a mailbox; The Virtual Interface Bridge gave a class a way to reach real pins. This page connects the two: a…
The Monitor
From Simple to Layered named this as the biggest structural gap in SystemVerilog's own capstone: no independent component whose only job is watching the…
The Reference Model
The monitor produces a stream of observed transactions. Deciding whether any of them were actually correct needs an independent prediction of what should…
Testbench: The Scoreboard
The monitor observes; the reference model predicts. The scoreboard is the component that actually puts the two together and decides pass or fail.
Assertion-Based Checking
Concurrent Assertions named this topic directly as where scoreboard-based checking gets a complementary strategy: assertion-based verification (ABV)…
The Environment
Every component built so far — generator, driver, monitor, reference model, scoreboard — exists independently, with no single place that owns building and…
The Test
The Environment can be built and launched in two lines. This page is where that actually happens — and where the open problem it left behind, deciding…
Functional Coverage Integration
The scoreboard answers "was the DUT's behavior correct." It says nothing about whether the test actually exercised enough of the FIFO's behavior to be a…
Configuration and Reuse
Every component across this topic has been built once, for one test. Real verification needs many tests reusing the same environment with different…
Limits of Hand-Rolled Testbenches
Three real problems surfaced across this topic, each one hit directly rather than described abstractly. This page takes stock of exactly those three, and…
Example Walkthrough: A FIFO Testbench
Sections A through E built this exact testbench piece by piece — transaction, generator, driver, monitor, reference model, scoreboard, an assertion-based…