Example Walkthrough: Synthesizing the PWM Register Block
This capstone is the third time this exact DUT has been the subject of a capstone on this site — UVM's RAL section built a register model for it, UPF's own capstone gave it real power domains, isolation, and retention. This page gives it what both of those assumed already existed: an actual gate-level netlist, synthesized from its RTL, end to end through every phase this topic covered.
The RTL going in
The PWM's CTRL, PERIOD, DUTY, and STATUS registers, plus the control logic that drives the actual PWM output waveform from PERIOD/DUTY — ordinary RTL, no different in kind from any other block Verilog and SystemVerilog already taught how to write.
Elaboration and technology-independent optimization
Elaboration resolves the register bit-widths and the comparator logic that drives PWM output generation into a generic internal representation. Technology-independent optimization finds real structure worth factoring here: the address-decode logic feeding all four registers shares comparison terms (checking address bits against 0x00/0x04/0x08/0x0C) that a kernel-based factoring pass would recognize as common sub-expressions worth sharing, rather than four independent comparators repeating the same address-bit checks.
Technology mapping
Technology mapping covers the now-optimized, still-abstract network with real cells from the library — the shared address-decode logic becomes real AOI/OAI cells chosen specifically because they matched that structure efficiently; the register bits themselves map to real flip-flop cells, selected in whatever drive strength the timing constraints below actually justify.
SDC constraints and timing-driven optimization
create_clock -period 4 -name clk [get_ports clk]
set_input_delay -clock clk -max 0.6 [get_ports {addr wdata wr_en}]
set_output_delay -clock clk -max 0.6 [get_ports {rdata}]
A 4ns period (250MHz) with real I/O delays budgeted on both sides. Timing-driven synthesis reads this before optimization even begins — the address-decode path feeding rdata is exactly the kind of path this constraint set makes worth watching, and if slack there is tight, that's precisely where a faster cell variant gets spent rather than everywhere uniformly.
Clock gating
CTRL, PERIOD, and DUTY only actually need to update on a write to that specific register — exactly the shared-enable pattern Clock Gating looks for. A synthesis tool recognizes this and inserts a gating cell per register bank, so each one's flops see zero clock toggling — zero dynamic power — on every cycle that isn't a write to that specific register. STATUS, being read-only and continuously driven from live hardware state, gets no such gating — there's no enable condition to gate on.
Reading this block's own QoR summary
Synthesis Outputs and Handoff named WNS and TNS as the two headline numbers a real report_qor-style summary prints — here's what that summary plausibly looks like for this exact, small register block, run against the 4ns/250MHz constraint above:
report_qor: pwm_reg_block
WNS (Worst Negative Slack) : 0.00 ns
TNS (Total Negative Slack) : 0.00 ns
Violating Paths : 0
Total Cell Area : 842 um^2
Critical Path Logic Levels : 6 (addr decode -> AOI mux -> rdata)
A clean WNS/TNS of 0.00 here isn't a coincidence for a block this small — four registers and an address decoder have a genuinely short critical path, and the 4ns budget with 0.6ns of I/O delay already carved out on each side leaves real slack to work with. This is exactly the outcome the PPA tradeoffs page's power-delay-product discussion described in the abstract, made concrete: a design with margin to spare doesn't need the tool to reach for the fastest, largest cell variant everywhere, which is part of why clock gating (below) is worth applying here — there's timing budget to spend on power savings rather than needing every last picosecond for speed.
What comes out
A real gate-level netlist, an SDF file with this specific netlist's characterized delays, the same SDC passed forward, and timing/area/power reports — exactly what Synthesis Outputs and Handoff described.
Closing the loop across all three topics
This is the same PWM whose UPF already gave it a power domain, isolation, and retention on CTRL/PERIOD/DUTY. The netlist this page just produced is exactly what Property and Equivalence Checking would prove matches the original RTL, and exactly what Gate-Level Simulation & X-Propagation would run, with this SDF, to catch anything RTL-level simulation couldn't see. Three separate topics — UVM (the register model), UPF (the power intent), Logic Synthesis (the netlist) — each did real, distinct work on the identical block, and Verification's already-shipped pages are what tie all three together into one coherent, complete verification story.
The synthesis flow, standard cell libraries, technology-independent optimization, technology mapping, SDC authoring, timing-driven synthesis, PPA tradeoffs, clock gating, and the handoff into already-shipped Verification content — 11 pages, applied here to one real, complete example. With this, Logic Synthesis joins every other topic on SiliconAcademia as a finished curriculum.