The Synthesis Flow

RTL goes in; a gate-level netlist comes out. Between those two points, a real synthesis tool runs through four distinct phases, each producing a representation the next phase actually needs — not one undifferentiated transformation.

The four phases

• Elaboration — the RTL is parsed, parameters and generate blocks are resolved to their concrete values, and the design is translated into a generic internal representation: primitive logic, arithmetic blocks, registers, memory, and recognized FSM patterns. This is the same parsing step that has to correctly resolve every construct Verilog and SystemVerilog taught — a generate loop or a parameterized width has to be fully resolved before any optimization can even begin.
• Technology-independent optimization — the elaborated design gets restructured using generic gates (AND, OR, NOT) with no relationship to any real, fabricable cell yet. This is where the actual logic minimization happens — Section B covers exactly what techniques apply here, and why the two-level methods Digital Design taught don't scale to this step's real input size.
• Technology mapping — the generic network gets matched onto real cells selected from an actual standard cell library — "AND of three inputs" becomes a specific, real, physically-fabricable 3-input AND cell with known delay, area, and power, not an abstract Boolean operator anymore.
• Post-mapping, timing-driven optimization — once real cells are in place, a final incremental pass adjusts the actual netlist: inserting buffers on paths that need them, resizing cells (swapping in a faster or smaller variant of the same logical function) to meet the constraints supplied via SDC, covered later in Section B. Concretely, this pass is what's checking for and closing setup violations (data arriving too late before the capturing clock edge) and hold violations (data changing too soon after it) — the two timing-violation categories the SDC-driven constraints exist to prevent.

Why this order, and not some other

Each phase depends on what the previous one produced, in a way that makes running them out of order meaningless: technology-independent optimization can't restructure logic it hasn't elaborated yet; technology mapping can't select real cells for a network that's still tangled up in RTL-level constructs; timing-driven cleanup can't resize or buffer cells that don't exist yet, before mapping has chosen them. The netlist that finally emerges is the accumulated result of all four — not a single mechanical pass, but a pipeline where each stage's job is only possible because of what came before it.

Flat vs. hierarchical: how much of the design runs through the flow at once

The four phases above describe what happens to a design as it moves through synthesis — but for a large chip, "the design" isn't always synthesized as one undivided whole:

• Flat synthesis — the entire design, top module down through every leaf block, is elaborated and optimized together in one run. The tool has full visibility across every boundary, so it can restructure and optimize logic that spans what used to be separate blocks — genuinely better results are possible, at the cost of runtime and memory that scale with the whole chip's size, which stops being practical once a design gets large enough.
• Hierarchical (bottom-up) synthesis — leaf-level blocks are synthesized first, independently, and then marked dont_touch so the top-level run treats each already-synthesized block as a fixed, opaque unit rather than re-optimizing into it. This trades away the flat approach's whole-design optimization opportunities for a runtime/memory footprint that scales with one block at a time, not the whole chip — the standard tradeoff for designs too large to run flat at all. It also matches how large SoC projects are actually organized: each block-owning team can synthesize and sign off its own block independently, without needing visibility into every other team's internals.

Neither approach changes what the four phases themselves do — elaboration, technology-independent optimization, technology mapping, and timing-driven cleanup still happen the same way. What changes is the scope each run of that pipeline covers: the whole design at once, or one block at a time with earlier results locked in place.

What's next

Every remaining page in this topic covers one piece of this pipeline in depth. The next page starts with the library technology mapping actually draws from — without it, "map to real cells" has nothing real to map onto.