Standard Cell Libraries

The Synthesis Flow's technology mapping step needs something concrete to map onto — real, physically fabricable logic gates with known electrical behavior, not the abstract AND/OR/NOT a tool works with beforehand. That's a standard cell library: a large collection of pre-designed, pre-characterized logic cells a synthesis tool actually selects from.

What a cell library actually contains

A real library isn't just "an AND gate, an OR gate, a flip-flop." For nearly every logical function, it contains multiple variants — different drive strengths (a 1x inverter versus an 8x inverter, trading area/power for the ability to drive a larger load quickly) and different threshold-voltage flavors (a low-Vt cell that's fast but leaky, a high-Vt cell that's slow but leaks far less). This multiplicity exists specifically so technology mapping (Section B) and later timing-driven optimization have real choices to make — a path with slack to spare can use a small, low-power cell; a critical path can use a larger, faster one for the identical logical function.

Characterization: where the numbers actually come from

Every cell in the library has been characterized — simulated under real conditions to determine exactly how it behaves — before a synthesis tool ever sees it. Characterization runs across PVT corners (Process, Voltage, Temperature — the real manufacturing and operating variation a chip has to work correctly across) and, for each corner, typically across a matrix of input transition times (slew) and output loads — commonly six of each, producing 36 characterized points per cell, per corner. The result is a .lib file: a table of exactly how much delay, how much power, and how much area each cell takes, for the full range of conditions it might actually see in a real design.

one cell, one corner, one small slice of its full characterization table

              output load →
              0.5fF   1fF    2fF    4fF    8fF   16fF
  slew  50ps │ 12ps   14ps   18ps   26ps   42ps   74ps │
  (in)  100ps│ 18ps   20ps   24ps   32ps   48ps   80ps │
        150ps│ 24ps   26ps   30ps   38ps   54ps   86ps │
              (delay values, illustrative)

Without this table, a synthesis tool would have no way to actually know whether a chosen cell meets a timing constraint — it isn't guessing or estimating, it's looking up a real, pre-measured number for the exact load and slew that cell sees in this specific netlist.

Naming the corners: which one checks setup, which one checks hold

PVT corners aren't characterized once and reused everywhere — a real library ships separate .lib files per corner, and each corner has a conventional name built from how fast its transistors switch: FF (fast-fast, both N- and P-type transistors switching quickly — low temperature, high voltage), SS (slow-slow — high temperature, low voltage), and TT (typical-typical, the nominal middle case). A synthesis/STA run doesn't pick just one: setup checks are analyzed against the SS (slow) corner, where cell delays are at their longest and a signal is most likely to arrive too late; hold checks are analyzed against the FF (fast) corner, where cell delays are at their shortest and a signal is most likely to arrive too early. A design that's clean at both extremes is safe everywhere in between — checking only one corner would leave the other failure mode completely unverified.

Why this is exactly what Verification's GLS already assumes

Gate-Level Simulation & X-Propagation runs against "the actual post-synthesis netlist, with real cell delays back-annotated from an SDF file." Those cell delays are exactly the characterized numbers this page just covered — SDF (Standard Delay Format) is how the specific delay values a synthesized netlist's actual cells carry get communicated to a gate-level simulator, pulled from the same characterization data technology mapping used to select those cells in the first place. GLS isn't inventing timing information independently; it's using the library's own measured numbers.

What's next

With a real library established as what technology mapping selects from, Section B covers what happens before mapping — the technology-independent restructuring that decides what logical shape the network has, before any real cell gets chosen at all.