Programmable Logic Arrays: PLA & PAL
A ROM implements any function correctly, but pays for that generality with size that doubles per extra input, regardless of how simple the actual function is. Programmable logic arrays take a different approach: instead of a lookup table addressed by every possible input combination, they directly implement the AND-OR structure of a sum-of-products expression — which means, unlike a ROM, they benefit exactly as much from logic minimization as hand-built discrete gates do.
The PLA: two programmable arrays
A PLA (Programmable Logic Array) is built from two programmable planes in series: a programmable AND array that forms product terms from the inputs (and their complements), feeding a programmable OR array that sums selected product terms together into each output — a direct, physical realization of canonical SOP form from Boolean Algebra & Logic Gates:
"Programmable" here historically meant an actual fuse at every AND-input and every OR-input intersection — intact fuse means that connection exists, blown fuse means it doesn't — programmed once, the same one-time mechanism as the PROM from the previous page, though modern PLA-family parts use the same reprogrammable floating-gate or SRAM-configuration technology as EEPROM/Flash.
Crucially, a PLA's AND array width is finite — a real part offers some fixed number of product-term rows, not one per possible input combination like a ROM's 2ⁿ addresses. That means minimizing an expression down to fewer product terms — exactly the K-map work from Logic Minimization — directly translates into whether a given function fits in a specific PLA part at all, not just into how "elegant" the implementation is. This is the sharpest practical contrast with ROM-based implementation: a ROM doesn't care how many minterms a function has (it stores every address's answer regardless), while a PLA cares enormously.
The PAL: trading flexibility for speed and cost
A PAL (Programmable Array Logic) simplifies the PLA by making only the AND array programmable, with the OR array fixed — each output OR-gate is permanently wired to a specific, fixed subset of the AND array's product-term rows:
Losing OR-array programmability sounds like a pure downgrade, but a fixed OR array is smaller, faster (one less programmable interconnect stage to propagate a signal through), and cheaper to manufacture than a fully programmable one — and in practice, a design rarely needs to share one product term across many differently-configured OR gates the way full PLA generality would allow, so the lost flexibility costs less than the fixed structure saves. That tradeoff made PAL parts historically far more common in real designs than full PLAs, to the point that "PAL" became something close to a generic term for small programmable logic devices in general, the same way "Kleenex" outgrew its original narrow meaning.
A later variant, the GAL (Generic Array Logic), reworks PAL using the same electrically-erasable technology as EEPROM instead of one-time fuses — reprogrammable, functionally equivalent to a PAL, and effectively obsoleted PAL for new designs once it arrived, for the same in-system-rewritable reasons EEPROM displaced PROM on the previous page.
Comparing the three
| ROM | PLA | PAL | |
|---|---|---|---|
| AND array (address decode / product terms) | Fixed (full decoder, every combination) | Programmable | Programmable |
| OR array (output combination) | Fixed (full mux/routing to data) | Programmable | Fixed |
| Size scales with | 2ⁿ (input count) | Number of product terms actually used | Number of product terms actually used |
| Benefits from minimization? | No | Yes | Yes |
| Flexibility | Any function of n inputs, m outputs | Any SOP expression that fits the array | SOP expressions matching the fixed OR-array wiring |
All three sit on the same spectrum — how much of the two-plane AND-then-OR structure is fixed at manufacture versus programmable by the user — and all three predate, and directly motivate, the far more general programmable fabric covered next.
What's next
PLA and PAL parts implement two-level AND-OR logic directly, but real designs need multi-level logic, storage elements, and far more capacity than a handful of programmable product terms can offer. The next page covers FPGAs — where the lookup-table idea from ROM and the programmable-interconnect idea from PLA/PAL both reappear, scaled up by orders of magnitude and combined with the flip-flops from Section D, into a fabric capable of implementing an entire digital system.