Memory Fundamentals: RAM Organization & Timing

Every circuit so far has stored, at most, a handful of bits — a register, a counter's state, an FSM's state register. Real systems need to store far more: millions or billions of bits, organized so that any one of them can be found and accessed quickly. This page covers how storage scales from "a few flip-flops" to "an addressable memory array," starting from the storage cell itself.

RAM vs. ROM

RAM (Random-Access Memory) can be both read and written, at any address, in any order, with roughly equal access time regardless of which address is accessed (the "random" in the name — contrasted historically with sequential-access media like tape, not with anything statistical). ROM (Read-Only Memory) can only be read during normal operation; its contents are fixed at manufacture or programmed once through a separate process, covered on the next page. Both share the same addressing and organization concepts from this page — the difference is entirely in the storage cell and whether a write path exists at all.

RAM itself splits into two families based on how each bit is physically stored:

• SRAM (Static RAM) — each bit is a small latch, built from cross-coupled inverters (the same feedback-loop idea as the SR latch from Latches & Flip-Flops, just built from inverters instead of NOR gates), plus access transistors that connect the cell to the bit lines when its word line is selected:

        word line (WL)
             │
    ┌────────┴────────┐
    │                  │
   [T1]               [T2]      ← access transistors
    │                  │
    ▼                  ▼
  ┌───┐              ┌───┐
  │ Q  ├──────────────┤ Q' │    ← cross-coupled inverter pair
  └───┘              └───┘
    │                  │
  bit line (BL)      bit line' (BL')

A stored bit holds indefinitely as long as power stays on — no refresh needed, hence "static." The cost is size: six transistors per bit (two inverters, four transistors, plus two access transistors) is a lot of silicon area per bit compared to the alternative below, which is why SRAM is reserved for places where speed matters more than density — CPU caches and register files, not bulk storage.

• DRAM (Dynamic RAM) — each bit is a single capacitor plus a single access transistor: charged for a 1, discharged for a 0. One transistor per bit instead of six makes DRAM dramatically denser than SRAM for the same silicon area, which is why it's the technology behind main system memory. The cost: a capacitor leaks charge over time, so a stored bit decays and must be refreshed — read and rewritten — periodically (typically every few milliseconds) or the data is lost, hence "dynamic." That refresh overhead, plus the read/write access itself being slower than SRAM's direct latch access, is the fundamental density-vs-speed tradeoff that shapes the entire memory hierarchy in real systems: a small, fast SRAM cache sitting in front of a much larger, slower DRAM main memory.

Address, data, and control

Regardless of cell technology, every memory array presents the same three-signal-group interface to the rest of a system:

• Address bus — selects which location to access. An n-bit address bus can select 2ⁿ distinct locations, exactly the same "n bits address 2ⁿ things" relationship from the decoders in Multiplexers, Decoders & Comparators — and that's not a coincidence, because address decoding is a decoder, covered below.
• Data bus — carries the value being read or written, sized to the memory's word width (8, 16, 32, 64 bits, etc.).
• Control signals — at minimum, a chip select (enabling the memory) and, for RAM, a read/write signal choosing the direction of the data bus for that access.

Total capacity is address-space size times word width: an address bus wide enough to select 2ⁿ locations, each m bits wide, gives a memory of 2ⁿ × m bits — conventionally written as "2ⁿ words × m bits," the standard way memory capacity is specified on any datasheet.

Internal organization: the decoder connection

A memory array is physically laid out as a grid — rows and columns of storage cells — with the address split into a row address and a column address. The row address feeds a decoder (structurally identical to the decoder from Multiplexers, Decoders & Comparators) that asserts exactly one word line, activating every cell in that row simultaneously; the column address then selects which of those activated cells' bit lines actually reach the data bus, using the same MUX-based selection idea from that same page.

This row/column split is exactly why memory capacity is usually a power of 2 in both dimensions — a decoder-and-MUX addressing scheme naturally wants binary-sized arrays — and it's also why "the decoder" and "the MUX," introduced as small standalone building blocks two sections ago, turn out to be the entire addressing mechanism for memories many orders of magnitude larger than anything built from them so far.

Read and write timing

A memory read presents an address, and after some access time (the time for the row decoder to settle, the selected cells to drive their bit lines, and the column MUX to route the result to the data bus), valid data appears on the data bus — a real-world instance of the same combinational settling-time reasoning that underpinned clock-to-Q delay and the critical-path inequality back in Timing, Setup/Hold & Metastability, just applied to a much larger circuit.

A write additionally needs the data bus to be driven with the value to store and the write-enable control asserted for at least the array's minimum write pulse width — conceptually the same setup/hold discipline that governs any flip-flop, since each written storage cell is, underneath, exactly the kind of latch or capacitor-cell described above accepting a new value on a control edge.

What's next

RAM cells that can be written are only half the picture. The next page covers ROM — memory that's read-only during normal operation, the different ways its contents get programmed (from a factory mask to reprogrammable Flash), and a genuinely different way to think about it: a ROM isn't just storage, it's a mechanical implementation of the truth-table-to-canonical-form idea from Boolean Algebra & Logic Gates, built entirely out of an addressable array.