Introduction to Digital Design
Every chip — a microcontroller, a GPU, a network switch ASIC — is, underneath all the marketing language, a very large network of two-state switches wired together to compute something. Digital design is the discipline of deciding what that network should be: which gates, which flip-flops, which state machines, arranged so that a sequence of 1s and 0s in produces the correct sequence of 1s and 0s out, reliably, on every single clock edge, for the life of the part.
This topic covers that discipline from first principles — independent of any specific hardware description language. Verilog and SystemVerilog are how you'll express these designs in a way tools can simulate and synthesize, but the concepts here (what a flip-flop actually does, how to minimize a Boolean function, how to build a correct state machine) are the same regardless of which language or tool you use to capture them. Learn them here first, and the HDL topics become a matter of syntax, not new ideas.
Analog vs. digital
Every physical signal — voltage on a wire, in particular — is fundamentally analog: it can take on any value in a continuous range, and it changes continuously over time. Digital design gets its power from deliberately throwing that continuity away. Instead of caring about the exact voltage on a wire, a digital circuit only asks one question: is this signal closer to 0 or closer to 1?
That one simplification is what makes large-scale digital systems possible at all:
- Noise immunity. A wire sitting at 3.3V with some electrical noise on it is still unambiguously a "1" as long as the noise doesn't push it past a defined threshold. An analog system carrying the same noise would corrupt the actual value being represented.
- Composability. Because every gate's output is restored to a clean 0 or 1 before it becomes the next gate's input, you can chain thousands of gates together without the signal "degrading" the way an analog signal would over a long chain of amplifiers.
- Storage and reuse. A digital value can be captured in a flip-flop and held indefinitely, bit-exact, then copied, compared, or reused — the basis for everything from a single register to an entire memory array.
The cost is that digital design has to actively re-derive things analog circuits get "for free" — timing (a digital value is only meaningful at the instant something reads it) and precision (a digital number is only as accurate as its bit width lets it be). Most of what this topic covers is, in one way or another, how to manage that cost correctly.
Quantifying noise immunity: noise margin
"Noise immunity" isn't just a qualitative claim — it has a standard quantitative measure called noise margin, and it's worth knowing the vocabulary since it comes up constantly in datasheets and interviews. A logic family's electrical spec defines four threshold voltages:
- VIH — the minimum input voltage a receiving gate is guaranteed to interpret as a logic 1.
- VIL — the maximum input voltage a receiving gate is guaranteed to interpret as a logic 0.
- VOH — the minimum voltage a driving gate guarantees to output for a logic 1.
- VOL — the maximum voltage a driving gate guarantees to output for a logic 0.
Because a real driving gate's output is always better than the receiving gate's minimum requirement (VOH > VIH, and VOL < VIL), there's a cushion of voltage on each side that noise can eat into before a signal is misread. That cushion is the noise margin:
- High-state noise margin: NMH = VOH − VIH
- Low-state noise margin: NML = VIL − VOL
A larger noise margin means a design can tolerate more electrical noise — crosstalk, ground bounce, supply ripple — without a receiving gate misinterpreting the intended logic value. This is also why shrinking supply voltages (5V logic families down to sub-1V modern process nodes) is a real engineering tradeoff, not just a power-saving free lunch: lower supply voltages generally compress VOH−VOL, shrinking the noise margin along with it, which is part of why signal integrity gets harder to guarantee as technology nodes scale down.
Propagation delay, fan-in, and fan-out
Composability ("chain thousands of gates together") isn't free of cost, just free of signal degradation — every gate still takes a nonzero amount of time to respond to a change on its inputs, and that time is called propagation delay: the interval between an input changing and the corresponding output settling to its new value. Chain enough gates in series and their propagation delays add up, which is exactly why the number of gate levels between one flip-flop and the next matters for how fast a design can be clocked — a theme that returns in force once timing constraints and setup/hold analysis are covered later in this topic.
Two related numbers describe how a gate loads down, or is loaded down by, its neighbors:
- Fan-in — the number of inputs a gate has. A wider fan-in (say, an 8-input AND gate versus a 2-input one) generally increases that gate's own propagation delay, since more internal transistors are stacked in the signal's path.
- Fan-out — the number of gate inputs a single gate's output is driving. Every additional input it drives adds capacitance the driving gate has to charge and discharge on every transition, so a higher fan-out slows down that output's edges and, past a technology-specific maximum fan-out, can erode noise margin enough to risk a misread logic level downstream.
Neither number is something a digital designer sizes by hand in a modern flow — synthesis and physical design tools manage buffering and drive strength automatically — but both remain standard interview vocabulary precisely because they're the concrete, gate-level reason "just chain more logic together" isn't a free lunch: it costs delay, and past a point, it costs correctness.
Why two states, not three or more
It's worth asking explicitly why digital design settled on binary (two states) rather than some higher-radix scheme — ternary logic (three states) has been studied and even built in research silicon, and in principle could pack more information per wire, potentially reducing interconnect count. The reason binary won out, and stayed dominant, traces directly back to noise margin above: with only two states to distinguish, the voltage range between VOL and VOH can be split with a wide guard band on each side of the threshold, making misreads rare even with real electrical noise on the wire. Add a third state and that same voltage range has to be split into three regions instead of two, shrinking each region's own noise margin proportionally — the same noise that was comfortably tolerated in a two-state system becomes far more likely to cause a misread in a three-state one. Binary's simplicity — one threshold, two clean regions, wide margins — is precisely what let digital logic scale to billions of switching elements per chip while staying reliable; multi-valued logic remains a research and niche-application area rather than a mainstream replacement for exactly this reason.
Levels of abstraction
No one designs a modern chip one transistor at a time — the design is worked at several abstraction levels, each hiding the detail of the one below it:
| Level | What it deals with | Roughly corresponds to |
|---|---|---|
| Behavioral | What the circuit should do | An algorithm, a state machine's behavior |
| Register-transfer level (RTL) | Data moving between registers each clock cycle | Verilog/SystemVerilog code |
| Gate level | AND/OR/flip-flop primitives and their interconnect | Output of logic synthesis |
| Transistor / physical level | Actual devices, wires, and layout on silicon | Output of place-and-route, physical design |
This topic lives mostly at the top two levels: the Boolean logic and state-machine thinking that RTL is built from. That's a deliberate scope choice — it's also exactly the level at which most design mistakes are made or caught, well before a design ever reaches synthesis or physical implementation.
What this topic covers
Digital design fundamentals break down into a few tightly connected areas, in the order they're presented here:
- Number systems & codes — how digital hardware represents quantities (binary, hex), signed values (two's complement), and specialized encodings (Gray code, BCD) that solve specific hardware problems.
- Boolean algebra & logic minimization — the algebra that governs how gates combine, and the systematic techniques (Karnaugh maps) for turning a correct-but-wasteful expression into an efficient one.
- Combinational logic design — circuits whose output depends only on the current inputs: adders, multiplexers, decoders, and the general methodology for building any of them from a truth table.
- Sequential logic design — circuits with memory: latches, flip-flops, registers, and counters, plus the timing discipline (setup/hold, clock domains) that makes them behave predictably.
- Finite state machines — the standard way to design any circuit whose behavior depends on history, not just current inputs, built from the combinational and sequential pieces above.
Where this fits with the rest of the curriculum
Everything here is language-agnostic — it's the "what to build," not the "how to type it." Once a concept is solid here (say, a Moore-machine state diagram for a traffic-light controller), Verilog covers how to actually code that state machine as synthesizable RTL, and Verification / UVM cover how to prove the RTL you wrote matches the design you intended. Treat this topic as the foundation the other four are built on, not a substitute for any of them.
What's next
The next few pages build the representational foundation everything else depends on: how digital circuits represent numbers and information as bits in the first place, starting with number systems and base conversion.