Counters

A counter is a register that generates its own next value every clock cycle, without an external data input driving it — it counts. This page covers the two fundamentally different ways to build one (ripple vs. synchronous), two special-purpose structural variants (ring and Johnson counters), and the general design procedure for a counter that visits an arbitrary sequence of states.

Ripple (asynchronous) counters

The simplest possible counter chains T flip-flops (from Latches & Flip-Flops) so that each flip-flop's output clocks the next one, instead of every flip-flop sharing a single clock:

Each T flip-flop is wired to always toggle (T tied to 1), so Q0 toggles on every input clock edge — dividing the clock frequency by 2 — Q1 toggles on every Q0 falling edge (dividing by 2 again), and so on. The result is a natural binary count on Q3 Q2 Q1 Q0, and the structure generalizes directly to any modulus: an n-flip-flop ripple counter counts 0 to 2ⁿ−1 and wraps around, with each stage dividing the previous stage's frequency by 2 — which is exactly why this circuit is also called a divide-by-2ⁿ counter and shows up constantly in clock-division circuits, independent of whether anyone actually cares about it "counting."

The name "ripple" describes its critical weakness: because each flip-flop is clocked by the previous flip-flop's output rather than by a shared clock, a change doesn't reach Q3 instantly — it has to propagate, one clock-to-Q delay at a time, through FF0, then FF1, then FF2, then FF3. For a brief window after the input clock edge, the intermediate count values are not all simultaneously valid — an external circuit sampling all four bits at once during that ripple window can see a transient, incorrect value that was never a real count state (e.g. 0111 briefly appearing while Q3 Q2 Q1 Q0 is rippling from 0011 to 0100). That glitch risk, plus the accumulated delay across many stages capping how fast the counter can run, is why ripple counters are essentially never used in real synchronous designs beyond simple clock-division utility circuits.

Synchronous counters

A synchronous counter fixes both problems by clocking every flip-flop from the same shared clock — exactly like the parallel register from the previous page — and instead computing each flip-flop's next-state input with combinational logic derived from the current count value, so every bit updates simultaneously on the same edge:

Each stage toggles only when all lower-order bits are 1 — exactly the carry condition of binary counting (a bit flips only when every bit below it is about to roll over from 1 to 0), computed directly with AND gates instead of relying on a rippling chain of clock edges to enforce it structurally. Because every flip-flop samples on the same clock edge, there's no ripple delay and no transient invalid output — the whole count value changes atomically. This is the standard counter structure in real synchronous designs; ripple counters only remain useful when frequency division, not a clean simultaneous count value, is the actual goal.

Mod-N counters

A plain n-bit binary counter is a mod-2ⁿ counter: it counts through all 2ⁿ states before wrapping back to 0. Real designs frequently need a count range that isn't a clean power of 2 — a decade (mod-10) counter for a digit display, or a mod-60 counter for seconds-within-a-minute. The standard technique layers a small amount of extra logic on top of the ordinary synchronous binary counter rather than redesigning it from scratch: use ⌈log₂N⌉ flip-flops (enough to reach at least N), let the counter increment normally, and add a comparator (or a decoder tap) that detects the target count N−1 and forces a synchronous reset to 0 on the following clock edge instead of letting the counter continue incrementing into N, N+1, ... up toward its natural 2ⁿ−1 wraparound. A mod-10 counter, for example, needs 4 flip-flops (since 2³=8 is too few states but 2⁴=16 is enough), counts 0000 through 1001 (0–9), then resets to 0000 instead of continuing to 1010.

Ring and Johnson counters

Two structural variants reuse the shift-register wiring from the previous page instead of binary counting logic, trading count range for simplicity of decoding:

Ring counter — a shift register with its serial output fed directly back into its serial input, initialized with a single 1 circulating through otherwise-0 flip-flops:

n flip-flops, n states.

An n-flip-flop ring counter has exactly n valid states, each with a single bit set — which means "what state am I in" is directly readable off a single flip-flop's output with no decoding logic at all, unlike a binary counter where identifying a specific count value needs an AND gate reading multiple bits. The tradeoff is state efficiency: n flip-flops give only n usable states, versus 2ⁿ for a binary counter of the same width — and a ring counter has no built-in way to recover if a glitch or power-up ever leaves it with zero or more than one bit set, since "exactly one 1" is an invariant the initial load has to establish, not one the circuit enforces afterward.

Johnson counter (twisted-ring counter) — identical shift-register wiring, but the complement of the last stage feeds back into the first stage instead of the last stage's raw value:

An n-flip-flop Johnson counter cycles through 2n states rather than n — doubling the ring counter's state count for the same flip-flop cost — at the price of needing a simple two-input decode (rather than a single flip-flop tap) to identify most individual states. Both variants show up in practical designs anywhere a clean, glitch-free one-hot or near-one-hot sequence is more valuable than binary-counting density — sequencing control signals in a state machine's datapath, or generating evenly-spaced clock phases, are typical uses.

Designing a counter for an arbitrary sequence

Ripple, synchronous binary, ring, and Johnson counters all follow a fixed, predetermined sequence by construction. Building a counter for an arbitrary sequence — say, 0 → 2 → 5 → 3 → 0 → ... in that specific order, skipping every other value — needs the general combinational design methodology from Combinational Logic Design, applied to next-state logic instead of a stateless function:

1. State table: list every current state and the specific next state it must transition to (from the desired sequence).
2. Flip-flop count: ⌈log₂(number of states)⌉ flip-flops, enough to encode every state as a unique bit pattern.
3. Excitation table: for each flip-flop and each current-state-to-next-state transition, work out what that flip-flop's input (D, or J/K if using JK flip-flops) needs to be to cause exactly that transition — for a D flip-flop this step is trivial (D = the next-state bit value directly, since a D flip-flop's next output is just whatever D was), which is the main practical reason D flip-flops dominate real designs over JK.
4. Minimize: treat each flip-flop's required input as its own Boolean function of the current state bits, and minimize it with a K-map exactly as in Logic Minimization — unused state codes (if the state count isn't a clean power of 2) can be treated as don't-cares here, the same don't-care exploitation from that page.
5. Implement: wire the minimized combinational logic to each flip-flop's input, sharing the same clock across all flip-flops, exactly like the synchronous binary counter above — the binary counter's T0=1, T1=Q0, T2=Q0·Q1, ... logic derived earlier in this page is nothing more than the output of this exact procedure applied to the specific sequence "count up in binary."

This procedure is completely general — it's the same one used to design the state-transition logic of a full finite state machine, which is exactly where the curriculum goes next.

What's next

Counters are a state machine with a fixed, predetermined sequence and no external control over which state comes next. The final section generalizes that idea fully: finite state machines, where the next state depends on both the current state and external inputs, giving a circuit the ability to make decisions based on its history — the concept that ties together everything covered since Boolean Algebra & Logic Gates.